Building a satellite navigation receiver on FPGA technology combined with ARM to serve special applications

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Authors

  • Nguyen Ngoc Thai (Corresponding Author) Institute of Electronics, Academy of Military Science and Technology
  • Pham Thanh Cong Institute of Electronics, Academy of Military Science and Technology
  • Dang Thi Thuy Bien Institute of Electronics, Academy of Military Science and Technology

DOI:

https://doi.org/10.54939/1859-1043.j.mst.97.2024.177-180

Keywords:

GNSS; GPS receiver; ZYNQ; FPGA; ARM.

Abstract

This paper proposes a solution to build a satellite navigation receiver based on FPGA technology combined with ARM. The proposed solution is based on classic methods and algorithms combined with a number of self-developed auxiliary algorithms implemented on self-designed and manufactured hardware. Signals from satellites are received by the frontend chip, then processed and given positioning results by the backend block, which is implemented by self-designed and manufactured hardware with the core of the Zynq chip. In doing so, satellite navigation receivers have a lot of flexibility and, most importantly, overcome some of the limitations that manufacturers of commercial positioning receiver chips have locked. In addition, the research results are also a premise for designing and manufacturing satellite positioning receiver chips for special applications as well as for Vietnam's own satellite positioning system in the future.

References

[1]. “European GNSS (Galileo) Open Service Signal In Space Interface Control Document (OS SIS ICD) Issue 1,” European Union/European GNSS Supervisory Authority (GSA), Tech. Rep., (2010).

[2]. “Fully integrated RF front-end receiver for GPS applications, STA5620 Data Sheet,” STMicroelectronics, (2008).

[3]. “Single-Chip Global Positioning System Receiver Front-End, MAX2742 Data Sheet,” Maxim, (2008).

[4]. G. Rivela, P. Scavini, D. Grasso, M. Castro, A. Calcagno, G. Avellone, A. Di Mauro, G. Cali, and S. Scaccianoce, “A low power RF front-end for L1/E1 GPS/Galileo and GLONASS signals in CMOS 65nm technology,” in Localization and GNSS (ICL-GNSS), 2011 International Conference on, pp. 7 –12, (2011).

[5]. N. Qi, Y. Xu, B. Chi, Y. Xu, X. Yu, X. Zhang, and Z. Wang, “A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS,” in Custom Integrated Circuits Conference (CICC), 2011 IEEE, pp. 1 –4, (2011).

Published

25-08-2024

How to Cite

Nguyen, N. T., Phạm Thành Công, and Đặng Thị Thùy Biên. “Building a Satellite Navigation Receiver on FPGA Technology Combined With ARM to Serve Special Applications”. Journal of Military Science and Technology, vol. 97, no. 97, Aug. 2024, pp. 177-80, doi:10.54939/1859-1043.j.mst.97.2024.177-180.

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