Improved performance of sonobuoys based on open source RISC-V SoC microprocessor technology
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https://doi.org/10.54939/1859-1043.j.mst.101.2025.56-63Keywords:
Risc-V Rocket; SoC; PTA-18; Arty-A7100T; Chisel; Acoustic Identification.Abstract
This paper presents a SoC design solution using Rocket core supporting open source RV32GC RISC-V instruction set, verifying the design on pre-silicon platforms which are Vivado FPGAs. The SoC system includes Rocket RISC-V core integrating peripheral blocks UART, SPI, RAM, ROM, GPIO, TILELINK BUS and a SonarDetect block (custom hardware developed by the user). This solution is applied to replace the central processor of the PTA-18 sonobuoy [1],develop and upgrade the target identification feature compared to the old design. SonarDetect is a new user design block (Custom Hardware) that detects the signals of local sonar targets, compares with the given database to identify the target. The design is tested and implemented on the Arty-A7 100T FPGA development kit and aims at the next goals of smartening and chip-izing the buoy control circuit.
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