Enhancing performance of GaN MMIC power amplifiers through transistor sizing and bias voltage optimization
DOI:
https://doi.org/10.54939/1859-1043.j.mst.IITE.2025.62-71Keywords:
GaN HEMT; Gate width; Bias voltage; Power amplifier; Ku_band; WIN NP25; Loadpull.Abstract
The paper presents a method for optimizing bias voltage and transistor size to improve power conversion efficiency (PAE) and output power in high-power amplifiers using GaN MMIC technology. Using simulation with the MP2500S transistor model in the WIN NP25 technology library on ADS software, the paper analyzed the effects of different VGS, VDS voltage levels and gate sizes on PAE, output power and Gain. The simulation and analysis results are applied to satellite communication uplink amplifiers (14 GHz ÷ 14.5 GHz) with gate width configurations from 2×75 µm to 8×125 µm. The results show that, with appropriate gate width, the selection of bias point in AB mode can significantly improve PAE while still ensuring the required Pout. However, the study also shows that excessive gate width expansion can reduce performance due to the trapping effect, parasitic leakage current and self-heating effect. The paper proposes a method to investigate and select the optimal transistor size and bias voltage in GaN PA design, particularly for Ku-band applications (12÷18 GHz) requiring high power and efficiency. This study contributes to improving the performance of GaN HEMT in power electronics applications.
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