Designing and simulation a 15-bit successive approximation register analog-to-digital converter
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https://doi.org/10.54939/1859-1043.j.mst.87.2023.1-8Keywords:
Analog-to-digital converters; Successive approximation register; Binary weighted with attenuation capacitor.Abstract
Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.
References
[1]. P. Fiedler, R. Mühle, S. Griebel, P. Pedrosa, C. Fonseca, F. Vaz, F. Zanow, and J. Haueisen, “Contact pressure and flexibility of multipin dry EEG electrodes” IEEE Trans. Neural Systems and Rehabilitation Engineering., vol. 26, no. 4, pp. 750–757, (2018). DOI: https://doi.org/10.1109/TNSRE.2018.2811752
[2]. X. T. Pham, N. T. Nguyen, V. -N. Nguyen and J. -W. Lee, “Area and Power-Efficient Capacitively-Coupled Chopper Instrumentation Amplifiers in 28 nm CMOS for Multi-Channel Biosensing Applications,” in IEEE Access, vol. 9, pp. 86773-86785, (2021). DOI: https://doi.org/10.1109/ACCESS.2021.3087737
[3]. X. T. Pham, V. -N. Nguyen, J. -S. Kim and J. -W. Lee, “A 0.52 μW, 38 nV/√Hz Chopper Amplifier With a Low-Noise DC Servo Loop, an Embedded Ripple Reduction Loop, and a Squeezed Inverter Stage,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 6, pp. 1793-1797, (2021). DOI: https://doi.org/10.1109/TCSII.2020.3045491
[4]. B. Murmann, "The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories," in IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 58-66, (2015). DOI: https://doi.org/10.1109/MSSC.2015.2442393
[5]. Y. Chen et al., "Split capacitor DAC mismatch calibration in successive approximation ADC," 2009 IEEE Custom Integrated Circuits Conference, pp. 279-282, (2009). DOI: https://doi.org/10.1109/CICC.2009.5280859
[6]. A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, pp. 246-610, (2008). DOI: https://doi.org/10.1109/ISSCC.2008.4523149
[7]. Y. Li, and Y. Lian, “Improved binary-weighted split-capacitive-array DAC for high-resolution SAR ADCs”, Electronics Letter, 50, (17), pp. 1194–1195, (2014). DOI: https://doi.org/10.1049/el.2014.1752
[8]. N. Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rate resolution scalable SAR ADC for wireless sensor node,” IEEE J. SolidState Circuits, vol. 42, no. 6, pp. 1196–1205, (2007). DOI: https://doi.org/10.1109/JSSC.2007.897157
[9]. S. Gambini and J. Rabaey, “Low-power successive approximation converter with 0.5 supply in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2348–2356, (2007). DOI: https://doi.org/10.1109/JSSC.2007.906210
[10]. Md.Kareemoddin, A. Ashok Kumar, Dr. Syed Musthak Ahmed, “Design of low power SAR ADC in Biomedical Applications”, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2, Issue 7, (2013).
[11]. Saberi, M., Lotfi, R., Mafinezhad, K., and Serdijn, W.A.: “Analysis of power consumption and linearity in capacitive digital-to-analog converters used in successive approximation ADCs”, IEEE Trans. Circuits Syst. I, 58, (8), pp. 1736–1748, (2011). DOI: https://doi.org/10.1109/TCSI.2011.2107214
[12]. H. Gao et al., “HermesE: A 96-channel full data rate direct neural interface in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1043–1055, (2012). DOI: https://doi.org/10.1109/JSSC.2012.2185338
[13]. T. Wakimoto, H. Li, and K. Murase, “Statistical analysis on the effect of capacitance mismatch in a high-resolution successive-approximation ADC,” IEEJ Transactions on Electrical and Electronic Engineering, 6(S1), S89–S93, (2010). DOI: https://doi.org/10.1002/tee.20625
[14]. B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC," in IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, (2007). DOI: https://doi.org/10.1109/JSSC.2007.892169
[15]. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guang-Ying Huang, "A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS," 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, pp. 80-81,81a, (2009). DOI: https://doi.org/10.1109/ISSCC.2009.4977317
[16]. Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian, “A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing”, 2019 IEEE transactions on Circuits and Systems I: Regular Papers, vol. 66, pp.477-488, (2018). DOI: https://doi.org/10.1109/TCSI.2018.2859837
