A design strategy for analyzing signal integrity in DDR3 bus of high speed embedded systems
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https://doi.org/10.54939/1859-1043.j.mst.CAPITI.2024.75-81Keywords:
Signal Integrity; PCB; DDR3; Trace Impedance.Abstract
A complex modern embedded system using a multi-core Central Processing Unit (CPU) toward a compact integrated design in a single Printed Circuit Board (PCB). One of the biggest challenges of the design is to meet the Signal Integrity for high speed Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3) bus. A typical strategy to solve the challenge is the simulation on the computer, but this is not always an effective solution as has a gap between simulation software and practical PCB. The gap is correlated to localized changes in copper density within the PCB and characterization of heterogeneous materials in PCB that could lead to differences in the real PCB. The purpose of the research presents an analysis methodology to design DDR) memory interfaces in high speed embedded systems, related to Signal Integrity and the impact of copper density on PCB trace impedances to overcome these challenges. Moreover, the presented design methodology is also applied to the next generation DDR as well as other styles of CPU.
References
[1]. W. Feng, L. Kai, and G. Ze, “Investigation of DDR T-Topology Port Resistance,” in 2020 IEEE 9th Joint International Information Technology and Artificial Intelligence Conference (ITAIC), Chongqing, China: IEEE, pp. 98–108, (2020). doi: 10.1109/ITAIC49862.2020.9338836. DOI: https://doi.org/10.1109/ITAIC49862.2020.9338836
[2]. Feng Wu, “The signal integrity simulation in the mobile phone design,” in 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility, Beijing, China: IEEE, pp. 52–55, (2010). doi: 10.1109/APEMC.2010.5475493. DOI: https://doi.org/10.1109/APEMC.2010.5475493
[3]. N. Bhagwath et al., “SI analysis of DDR bus during read/write operation transitions,” in 2017 IEEE 21st Workshop on Signal and Power Integrity (SPI), Lake Maggiore, Italy: IEEE, pp. 1–4, (2017). doi: 10.1109/SaPIW.2017.7944018.. DOI: https://doi.org/10.1109/SaPIW.2017.7944018
[4]. S. S. George, S. Sivanantham, S. Pawar, and R. Vikram, “Signal Integrity and Power Integrity Challenges in Embedded Computing Boards,” in 2018 15th International Conference on ElectroMagnetic Interference & Compatibility (INCEMIC), Bengaluru (Bangalore), India: IEEE, pp. 1–4, (2018). doi: 10.1109/INCEMIC.2018.8704606. DOI: https://doi.org/10.1109/INCEMIC.2018.8704606
[5]. K. X. Cai, S. Y. Ji, M. Dakroub and R. Chakraborty, “Signaling margin oriented LPDDR PDN design with SIPI synthesis methodology,” 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), Ottawa, ON, Canada, pp. 50-53, (2016), doi: 10.1109/ISEMC.2016.7571602. DOI: https://doi.org/10.1109/ISEMC.2016.7571602
[6]. J. Chandrasekhar and Y. Shim, “Noise transfer from receiver to transmitter circuits of tranceivers through power supply network(PDN),” in 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC), Raleigh, NC, USA: IEEE, pp. 485–490, (2014). doi: 10.1109/ISEMC.2014.6899021. DOI: https://doi.org/10.1109/ISEMC.2014.6899021
[7]. C.-K. Chan et al., “Signal/Power Integrity Co-Simulation of DDR3 Memory Module,” in 2018 IEEE International Conference on Computational Electromagnetics (ICCEM), Chengdu: IEEE, pp. 1–3, (2018). doi: 10.1109/COMPEM.2018.8496538. DOI: https://doi.org/10.1109/COMPEM.2018.8496538
[8]. P. J. Pupalaikis, S-Parameters for Signal Integrity, 1st ed. Cambridge University Press, (2020). doi: 10.1017/9781108784863. DOI: https://doi.org/10.1017/9781108784863
[9]. G. A. Brist, J. Krieger, and D. Willis, “PCB Trace Impedance: Impact of Localized PCB Copper Density”. pp. 1–9, Intel Corp, (2012).
[10]. JEDEC Standard, JESD79-3F, (2010), www.jedec.org
