Hardware-efficient matrix multiplication core optimization for edge AI on FPGA
DOI:
https://doi.org/10.54939/1859-1043.j.mst.IITE.2025.123-130Keywords:
IP cores; Matrix multiplication; FPGA-CNN; MAC; Vivado-Vitis.Abstract
This paper presents an optimization approach for matrix multiplication IP cores on FPGA by transforming convolution operations into matrix multiplications. The proposed method leverages parallel computation combined with simultaneous data loading within the same processing cycle, thereby reducing memory requirements and computational latency. Furthermore, casting the output data from 64-bit to 32-bit effectively shrinks the output buffer, resulting in significant hardware resource savings. Simulation results on ModelSim and Vivado–Vitis demonstrate that the design achieves higher computational efficiency and resource utilization compared to traditional implementations, while maintaining stable processing time. This work contributes to the design of CNN inference accelerators on FPGA for edge AI applications, where resource constraints and power consumption are critical factors..
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